ETS'07 - Panel Sesions only

- Complete Program
- May 20th, 2007 only
- May 21st, 2007 only
- May 22nd, 2007 only
- May 23rd, 2007 only
- Presentation Sessions only
- Vendor Sessions only
- Posters Sessions only
- Panels Sessions only
- Tutorials only

May 20th, 2007

10:30-11:00 Coffee 

12:30-13:30 Lunch 

15:00-15:30 Coffee 

May 21st, 2007

10:30-11:00 Coffee 

12:30-14:00 Lunch 

18:00-19:30 Panel Session 6A: Logic BIST and Test-Data Compression: Friends or Foes?

Organizers
- Ben Bennetts : Bennetts Associates, UK
- Erik Jan Marinissen : NXP Research, NL

Moderator
- Ben Bennetts : Bennetts Associates, UK

Abstract:  Just a few years ago, Logic BIST was presented as the one and only solution to virtually all test challenges: growing ATE costs, growing test application times, difficult test access to deeply embedded cores, etc. However, suddenly, in 2001, before mainstream acceptance of Logic BIST, the first commercial Test Data Compression tool was launched. This, and similar TDC products, seemed to have quickly gained foothold in the DfT market. This panel will address the following questions: Did TDC tools actually erode the market for Logic BIST tools? How do TDC and Logic BIST compare, in benefits and costs? Is the success of TDC a temporary thing, while the long-term solution still has to come from Logic BIST? What are companies offering or using today, and how do they expect that to change in the medium- and long-term future? Is the DfT space per chip big enough for both approaches to co-exist?

Panelists
- Davide Appello : ST Microelectronics, Italy
- Friedrich Hapke : NXP Semiconductors, Germany
- Richard Illman : Cadence Design Systems, United Kingdom
- Steve Sunter : LogicVision, Canada
- Jürgen Alt : Infineon Technologies, Germany
- Janusz Rajski : Mentor Graphics, USA
- Tom Williams : Synopsys, USA

20:00-22:00 Dinner 

Location: Feierling
More detailed information can be found here.

May 22nd, 2007

12:30-14:00 Lunch 

May 23rd, 2007

11:00-12:30 Panel Session 13A: Error Tolerance: Are Good-enough Chips Good Enough?

Organizer
- Ilia Polian : Universität Freiburg, Germany

Moderator
- Ilia Polian : Universität Freiburg, DE

Abstract:  The advent of nanoscale technologies is leading to more and more errors, both hard and soft, showing up in the circuits. Known fault tolerance approaches can help in solving the problem, but often at an prohibitively high cost. Error tolerance is a novel paradigm stating that circuits containing defects, or good-enough (rather than perfect) chips, can operate in a way acceptable with respect to an application. First experiments demonstrated that a significant share of single-stuck-at faults in MPEG and JPEG devices lead to an acceptable performance. This panel will address the following questions: Is error tolerance a concept suited to achieve adequate yields in inherently unreliable nanoscale technologies? What are the implications of error tolerance on the design, test and verification flows? Is the market willing to accept good-enough chips? Is error tolerance applicable to hard or soft errors? What are the limitations?

Panelists
- Rob Aitken : ARM, USA
- Abhijit Chatterjee : Georgia Tech, USA
- Sandip Gupta : University of Southern California, USA
- John P. Hayes : University of Michigan, USA
- Jens Leenstra : IBM R&D, Germany

12:30-14:00 Lunch