linkETS'07 Logo

12th IEEE European Test Symposium

Convention Center, Freiburg, Germany

May 20-24, 2007



The tutorials of ETS'07 are part of the annual IEEE Computer Society TTTC Test Technology Educational Program (TTEP) 2007

The tutorials will take place on Sunday, May 20th, from 9:00 till 17:00. Tutorials will be held in the Katholische Akademielink , Wintererstr. 1. Please refer to the map for the location of the tuorial site (C on the map).


Tutorial registration is done via the ETS Registration Form.
Please find below the description of Tutorial 1 and Tutorial 2

Tutorial 1

  • Title:

    Practices in Analog, Mixed-Signal, and RF Testing

  • Presenters:

    Salem Abdennadher
    Intel Corporation
    1900 Prairie City Road, M/S FM6-4
    Folsom, CA 95630, USA
    Email: salem.abdennadher@intel.comlink
    Phone: 916-377-1632
    Fax: 916 854 1161

    Saghir A Shaikh
    Cadence Design Systems, Inc.
    5015 Santa Cruz Avenue, 307
    San Diego, CA 92107, USA
    Email: saghir@cadence.comlink
    Phone: 619-221-1919

  • Tutorial Summary:

    Most analog, mixed-signal and RF testing in industry today involves specification-based testing using Automatic Test Equipment (ATE). However, some companies employ alternative solutions to ATE testing that use DFT and BIST. This tutorial presents a brief overview of the industry practices in mixed-signal testing and RF testing. It includes testing examples of wired and wireless transceivers (an essential part of ultra high-speed networks). Plus, it discusses the testing challenges of System in Package (SiP), an emerging technology, and some of the feasible DFT solutions.

  • Intended Audience:

    This tutorial is most suitable for design, test and DFT engineers involved in actual implementation of mixed-signal and wireless devices and systems. The architects and engineering managers would also greatly benefit from this tutorial.

  • Tutorial Program:

    This tutorial intends to present the following:

    1. challenges involved in analog and RF testing
    2. basic specifications for analog and RF SoCs targeted for testing
    3. options available for testing the analog and RF devices
    4. the pros and cons of ATE-based, DFT, BIST techniques for analog and RF devices
    5. solutions of practical mixed-signal and RF devices
  • The tutorial will be divided into three major sessions as follows:

    1. Analog Specification Testing
      1. Understand traditional measurements for transceivers
        Receiver sensitivity, at-speed testing, eye diagram, intrinsic jitter, jitter transfer, jitter tolerance testing, and pulse template.
      2. ATE based techniques
      3. Transceivers testing/SERDES testing
      4. High speed interface testing
        PCI-Express and XAUI, etc.
    2. Analog DFT based techniques
      1. PLL testing
      2. Nyquist rate converter POR testing
      3. Delta sigma converter POR testing
      4. Equalizer testing
      5. Analog front-end testing
      6. Filters testing
      7. Mixers testing
      8. LNA testing
      9. ADC and DAC testing
      10. AGC testing
    3. RF Testing
      1. RF Specifications and Testing
        gain, power compression, TOI (Third-Order Intercept), harmonics, noise figure, phase noise, IQ mismatches, EVM, and ACPR (Adjacent Channel Power Ratio).
      2. Wireless radio building blocks
      3. Wireless products testing
      4. Wireless DFT solutions
      5. RF Production testing
      6. Testing of MIMO and SiP based system

  • Instructors biographies:

    Salem Abdennadher, Senior Staff DFX Engineer, Intel Corporation has fourteen years of experience in mixed-signal design and DFT. Soon after graduating with Masters from Oregon State University 1992, he joined the industry and has worked with a research lab in France, Motorola, Level One Communications and Intel. His recent publications and international patent filing in mixed-signal DFT/BIST range from Filter BIST and On-chip Jitter BIST, to mixed-signal behavioral modeling and noise extraction and prediction. Salem also has presented tutorials through TTEP at ATS'04, LATW'05, VTS'05, ITC'05, ITC'06 and DATE'07 and is an invited speaker for the ATS'05 industry challenges session.

    Saghir A. Shaikh, Ph.D., Senior Core Competency Technical Leader at Cadence Design Systems, a graduate of the University of Texas at Austin (96), Dr. Shaikh has eleven years of industrial experience in DFT at Intel Corporation, Sun Microsystems and Level One Communciations, Inc. He has authored more than a dozen research papers which are presented in various conferences such as ITC, ICCAD, and VTS. Saghir also has presented six tutorials through TTEP at ATS'04, LATW'05, VTS'05, ITC'05, ITC'06 and DATE'07 and is an invited speaker for the ATS'05 industry challenges session.

Tutorial 2:

  • Title:

    Statistical Screening Methods targeting "Zero defect"  IC Quality and Reliability

  • Presenters:

    Adit D. Singh
    Electrical & Computer Engineering
    Auburn University, AL 36849, USA
    Email: adsingh@auburn.edulink

  • Tutorial Summary:

    The wide variation in normal process parameters now being observed in advanced semiconductor processes can sometimes cause the electrical impact of subtle manufacturing defects to remain within the acceptable range during test, thereby masking defect detection. Such undetected manufacturing flaws can potentially cause functional failure under untested operating conditions; they can also behave as latent reliability defects that "grow" over time to cause early life failure. Test methodologies that target "zero-defect" product quality requirements must address such test escapes by using innovative statistical methods to screen out passing parts that have a significant likelihood of field failure. Advanced screening methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers -suspecting passing die in "bad" neighborhoods; and those that exploit the correlation in performance parameters on wafers -suspecting passing die that are performance outliers within local regions of the wafer. This tutorial will present screening methodologies that span both these categories, and illustrate their effectiveness using results from a number of recently published experimental studies on production circuits from IBM, Intel, LSI Logic, and NXP Semiconductor.

  • Intended Audience:

    Test and Reliability Engineers, Engineering Managers, Reliability and Quality Assurance Managers, Researchers and Research Students.

  • Instructors biographies:

    Adit D. Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, where he directs the VLSI Design and Test Laboratory. His technical interests span all aspects of VLSI design, test and reliability. He has published about one hundred fifty research papers, served as a consultant to several major semiconductor companies, and holds international patents that have been licensed to industry.
    Singh received the B.Tech from IIT Kanpur, and the M.S, and Ph.D. from Virginia Tech, all in Electrical Engineering. He is a Fellow of IEEE.