ETS'07 - May 21st, 2007

- Complete Program
- May 20th, 2007 only
- May 21st, 2007 only
- May 22nd, 2007 only
- May 23rd, 2007 only
- Presentation Sessions only
- Vendor Sessions only
- Posters Sessions only
- Panels Sessions only
- Tutorials only

May 21st, 2007

08:00-17:30 Symposium Registration

Location: Convention Center.
To find the location have a look at the map.

08:30-10:30 Session 1: Plenary Opening

Moderator
- Hans-Joachim Wunderlich : Universität Stuttgart, DE, ETS'07 Vice Program Chair

08:30-09:00 

Welcome Address
Bernd Becker : Universität Freiburg, Germany, ETS'07 General Chair

Technical Program Introduction
Zebo Peng : Linköping University, Sweden, ETS'07 Program Chair

Presentation of ETS'06 Best Paper Award
Erik Jan Marinissen : NXP Research, The Netherlands, ETS'06 Program Chair

09:00-09:45 Keynote

If It's All About Yield, Why Talk About Testing?
Rene Segers : NXP Semiconductors, The Netherlands

09:45-10:30 Invited Address

Electronics Design-For-Test: Past, Present and Future
Ben Bennetts : Bennetts Associates, United Kingdom

10:30-11:00 Coffee 

11:00-12:30 Session 2A: Fault and Defect Diagnosis

Moderators
- Janusz Rajski : Mentor Graphics, USA
- Laroussi Bouzaida : ST Microelectronics, FR

Adaptive Debug and Diagnosis Without Fault Dictionaries
Stefan HOLST · Hans-Joachim WUNDERLICH : Universität Stuttgart, Germany

Interconnect Open Defect Diagnosis with Minimal Physical Information
Chen LIU : University of Iowa, USA · Wei ZOU : Mentor Graphics, USA · Sudhakar M.REDDY : University of Iowa, USA · Wu-Tung CHENG · Sharma MANISH · Huaxing TANG : Mentor Graphics, USA

DERRIC: a Tool for Unified Logic Diagnosis
Alexandre ROUSSET · Alberto BOSIO · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France

08:30-10:30 Session 2B: Mixed Signal DFT and Test

Moderators
- Andrew Richardson : University of Lancaster, UK
- Seiji Kajihara : Kyushu Institute of Technology, JP

A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter
Erik SCHÜLER · Marcelo NEGREIROS : Universidade Federal do Rio Grande do Sul, Brazil · Pascal NOUET : LIRMM, France · Luigi CARRO : Universidade Federal do Rio Grande do Sul, Brazil

Reducing the Influence of DC Offset Drift in analog IPs using the Thue-Morse Sequence as Stimulus
Jan SCHAT : NXP, Germany

Using current testing to improve test coverage in mixedsignal IC testing
Yang ZHONG : RWTH Aachen University, Germany · Liquan FANG · Henk VAN DE DONK : NXP Semiconductors, The Netherlands

08:30-10:30 Vendor Session 2C: Advanced DFT Tools

Moderators
- Peter Muhmenthaler : Infineon Technologies, DE
- Einar J. Aas : Norwegian University of Science & Technology, NO

A Review of Power Strategies for DFT and ATPG
Richard ILLMAN · Brion KELLER · Sandeep BHATIA : Cadence, USA

ScanBurst - Scan Infrastructure and Environment for Highly Effective At-Speed Testing
Stephen PATERAS · Peter SHIELDS : LogicVision, USA

Realizing yield improvements with YieldAssist: High Volume Scan Diagnosis and Analysis
Brady BENWARE : Mentor Graphics, USA

12:30-14:00 Lunch 

14:00-15:30 Session 3A: NoC Testing

Moderators
- Gert Jervan : Tallinn University of Technology, EE
- Krishnendu Chakrabarty : Duke University, US

Test Configurations for Diagnosing Faulty Links in NoC Switches
Jaan RAIK · Raimund UBAR · Vineeth GOVIND : Tallinn University of Technology, Estonia

Optimization of NoC Wrapper Design Under Bandwidth and Test Time Constraints
Fawnizu Azmadi HUSSIN · Tomokazu YONEDA · Hideo FUJIWARA : Nara Institute of Science and Technology, Japan

How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes?
Xuan-Tu TRAN · Jean DURUPT · François BERTRAND : CEA-LETI, France · Vincent BEROULLE · Chantal ROBACH : INPG-LCIS, France

14:00-15:30 Session 3B: Advances in RF Test

Moderators
- Jochen Rivoir : Verigy, DE
- Abhijit Chatterjee : Georgia Tech, US

FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests
Ivo KOREN · Frank DEMMERLE · Roland MAY · Martin KAIBEL : Infineon AG, Germany · Sebastian SATTLER : Infineon Technologies, Germany

Digital Generation of Signals for Low Cost RF BIST
Marcelo NEGREIROS · Luigi CARRO · Altamiro SUSIN : Universidade Federal do Rio Grande do Sul, Brazil

Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives
Shaji KRISHNAN · René JONKER · Leon VAN DE LOGT : NXP Semicondutors, The Netherlands

14:00-15:30 Vendor Session 3C: Test Equipment and Solutions

Moderators
- Yervant Zorian : Virage Logic, US
- Gunnar Carlsson : Ericsson, SE

The FLEX Architecture - High Efficiency Multisite Test
Martin STADLER : Teradyne, Germany

Scalable System Platform for Cost Effective Mixed Signal Test Solutions
Bruce MacDONALD : LTX, USA

Solutions for Testing Complex SoCs
Martin FISCHER : Verigy, Germany

15:30-16:30 Session 4: Posters and Coffee Break

Primary Input Vectors to Eliminate from Random Test Sequences for Synchronous Sequential Circuits
Irith POMERANZ : Purdue University, USA · Sudhakar M.REDDY : University of Iowa, USA

Reducing Test Data Volume of Deterministic BIST Via Test-Point Insertion
Yang ZHAO · Dong XIANG : Tsinghua University, China · Krishnendu CHAKRABARTY : Duke University, USA

A Self-Correction Method for Change in Clock Signal Width
Yukiya MIURA : Tokyo Metropolitan University, Japan

On Improving Channel Utilization in Testing NoC-Based Systems
Jia LI : Chinese Academy of Sciences, China · Qiang XU : The Chinese University of Hong Kong, Hong Kong · Yu HU · Xiao-wei LI : Chinese Academy of Sciences, China

Logic Errors in CMOS circuits due to Simultaneous Switching Noise
Florence AZAÏS · Laurent LARGUIER · Michel RENOVELL : LIRMM, France

Towards a test vector independent test response analyser for NoCs
Kim PETERSEN : HDC AB, Sweden · Johnny ÖBERG : KTH, Sweden

Analysis of Random Testbench for Data-Dominated Hardware Descriptions
Iñigo UGARTE · Pablo SANCHEZ : Universidad de Cantabria, Spain

Accessibility to Embedded A/MS Cores: An Oscillation-Based S-R DFT
Rahebeh NIARAKI : Iran University of Science and Technology, Iran · Zainalabedin NAVABI : Northeastern University, USA · Sattar MIRZAKUCHAKI : Iran University of Science and Technology, Iran · Michel RENOVELL : LIRMM, France

Implementation of security extension for IEEE Std 1149.1 and analysis of possible attack scenarios
Franc NOVAK · Anton BIASIZZO : Jozef Stefan Institute, Slovenia

Pattern Generation for Composite Leakage Current Maximization
Ashesh RASTOGI · Kunal GANESHPURE · Alodeep SANYAL · Sandip KUNDU : University of Massachusetts, USA

16:30-18:00 Session 5A: Diagnosis and Debug

Moderators
- John P. Hayes : University of Michigan, US
- Bruno Rouzeyre : LIRMM, FR

Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips
Tao XU · Krishnendu CHAKRABARTY : Duke University, USA

Communication-centric SoC Debug using Transactions
Bart VERMEULEN · Kees GOOSSENS : NXP Semiconductors, The Netherlands · Remco VAN STEEDEN : University of Twente, The Netherlands · Martijn BENNEBROEK : Philips Research, The Netherlands

Debug Architecture of the En-II System-on-Chip
Bart VERMEULEN · Sjaak BAKKER : NXP Semiconductors, The Netherlands

16:30-17:30 Session 5B: Simulation and Verification

Moderators
- Franco Fummi : University Verona, IT
- Jaan Raik : Tallinn University of Technology, EE

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories
Olivier GINEZ : LIRMM, France · Jean-Michel DAGA : ATMEL, France · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France

Test Circuit for Functional Verification of Automatically Generated Cell Library
M. GOMEZ · A. SILVA · S. BAVARESCO · C. ALEGRETTI · G. SARTORI · L. ROSA Jr. : Universidade Federal do Rio Grande do Sul, Brazil · A. REIS : Nangate, USA · Renato RIBAS : Universidade Federal do Rio Grande do Sul, Brazil

16:30-18:00 Vendor Session 5C: Intelligent Test Flows

Moderators
- Bernd Koenemann : Visiting Professor, Universität Bremen, DE
- Jerzy Tyszer : Poznan University of Technology, PL

Multiple Benefit by Adaptive Testing
Gil BALOG : OptimalTest, Israel

New RF Test Technologies for lower cost and flexibility
Bill BURROWS : Aeroflex Test Solutions, United Kingdom

Enabling DUT-ATE Interaction
Frank GROSSMANN : SPEA, Germany

18:00-19:30 Panel Session 6A: Logic BIST and Test-Data Compression: Friends or Foes?

Organizers
- Ben Bennetts : Bennetts Associates, UK
- Erik Jan Marinissen : NXP Research, NL

Moderator
- Ben Bennetts : Bennetts Associates, UK

Abstract:  Just a few years ago, Logic BIST was presented as the one and only solution to virtually all test challenges: growing ATE costs, growing test application times, difficult test access to deeply embedded cores, etc. However, suddenly, in 2001, before mainstream acceptance of Logic BIST, the first commercial Test Data Compression tool was launched. This, and similar TDC products, seemed to have quickly gained foothold in the DfT market. This panel will address the following questions: Did TDC tools actually erode the market for Logic BIST tools? How do TDC and Logic BIST compare, in benefits and costs? Is the success of TDC a temporary thing, while the long-term solution still has to come from Logic BIST? What are companies offering or using today, and how do they expect that to change in the medium- and long-term future? Is the DfT space per chip big enough for both approaches to co-exist?

Panelists
- Davide Appello : ST Microelectronics, Italy
- Friedrich Hapke : NXP Semiconductors, Germany
- Richard Illman : Cadence Design Systems, United Kingdom
- Steve Sunter : LogicVision, Canada
- Jürgen Alt : Infineon Technologies, Germany
- Janusz Rajski : Mentor Graphics, USA
- Tom Williams : Synopsys, USA

18:00-19:00 Embedded Tutorial Session 6B: 

Moderator
- Patrick Girard : LIRMM, FR

Low Power Test
Nicola NICOLICI : McMaster University, Canada · Xiaoqing WEN : Kyushu Institute of Technology, Japan

Abstract  Excessive power during test affects the reliability of digital integrated circuits, test throughput and manufacturing yield. Numerous low power test methods have been investigated over the past decade and new power-aware automatic test pattern generation, design-for-test and test planning techniques have emerged. This embeded tutorial introduces the topic of low power test and it overviews the basic techniques and some recent advancements in this field.

20:00-22:00 Dinner 

Location: Feierling
More detailed information can be found here.