12th IEEE European Test Symposium
Convention Center, Freiburg, Germany
May 20-24, 2007
Call for Papers
Silicon Debug and Diagnosis
Keynote: If It's All About Yield, Why Talk About Testing?
Rene Segers, NXP Semiconductors, The Netherlands
Abstract This talk will discuss the evolution of test and diagnosis, in the broad sense, over the recent years as well as the outlook into the future. Test, as it was only recently a pure discriminator between good and bad, has gained significant more added value by acting also a feedback loop towards the manufacturing process of Integrated Circuits. Of course this feedback loop was already there, but was limited to information on test bin level from a tester. In the last couple of years, this has changed dramatically, and we are now able to pinpoint to circuit coordinates and /or to circuit structures as potential candidates for low yield causes. By linking this diagnosis information to in-line data, a more than direct link to a root cause in the fab can be achieved. And this is not the end of the story. By linking diagnosis to the layout one should be able to even stronger and quicker close the loop between Design, Manufacturing and Test. All of the above will be discussed in the talk, which in a sense could mean that the talk is all about DfX, Design for eXcellence...
Curriculum Vitae After having finished his studies at the Technical University of Eindhoven, and after the then regular period of military service, Rene Segers started his career at Philips Research. There he led the introduction of DfT in general and digital scan-test in particular into Philips. Since those early days he had various positions in Philips, including Consumer Electronics, the Centre for Manufacturing Technology and Philips Semiconductors. Last year, together with more than 30.000 others, he joined NXP semiconductors where he is now DfX program manager. Until a couple of years ago Rene also acted as a professor in test technology at the Technical University in Eindhoven.
Invited Address: Electronics Design-For-Test: Past, Present and Future
Ben Bennetts, Bennetts Associates, United Kingdom
Do you know how many ENIAC vacuum tubes were replaced
every day during its heyday? What did it teach us about Test, or Design-
For-Test? Did Eldred really invent the stuck-at fault model in 1959? Is
99.999% fault cover all it's cracked up to be or are we fooling ourselves?
Are we better off with 115% or even 80%? Where did Design-For-Test
come from? Where is it now? Where's it heading? Is it true that boundary
scan is the panacea of test? What are all these new Joint Test Action
Groups - Internal, System and compact? Are they boondoggles, or are
Curriculum Vitae Dr R.G. "Ben" Bennetts was an independent consultant in Design-For-Test (DFT), consulting in product life-cycle DFT strategies, and delivering on-site and open educational courses in DFT technologies. During his career, he worked for LogicVision, Synopsys, GenRad and Cirrus Computers. Between 1986 and 1993, he was a free-lance consultant and lecturer on Design-for-Test (DFT) topics. During this time, he was a member of JTAG, the organization that created the original IEEE 1149.1- 1990 Boundary-Scan Standard. He was a core-group member of IJTAG and SJTAG (and currently the SJTAG Chairman Emeritus), a co-founder and past Program Chair of the IEEE Board Test Workshop, a Steering Committee member of the IEEE European Test Workshop/Symposium for many years, founder of the IEEE European Board Test Workshop, and the founder and ex-Chairman of the IEEE's BTTAC organisation. During the period 1968-2006, he published over 100 papers plus three books on test and DFT subjects. He retired from all DFT teaching and most DFT consulting on 31 December, 2006.
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