linkETS'07 Logo

12th IEEE European Test Symposium

Convention Center, Freiburg, Germany

May 20-24, 2007


ETS'07 - Complete Final Program

- Complete Program
- May 20th, 2007 only
- May 21st, 2007 only
- May 22nd, 2007 only
- May 23rd, 2007 only
- Presentation Sessions only
- Vendor Sessions only
- Posters Sessions only
- Panels Sessions only
- Tutorials only

May 20th, 2007

08:00-14:00 Tutorial Registration

Location: Katholische Akademie.
To find the location have a look at the map.

09:00-10:30 Tutorials

More detailed information can be found here.

10:30-11:00 Coffee 

11:00-12:30 Tutorials

More detailed information can be found here.

12:30-13:30 Lunch 

13:30-15:00 Tutorials

More detailed information can be found here.

15:00-15:30 Coffee 

15:30-17:00 Tutorials

More detailed information can be found here.

15:00-18:30 Symposium Registration

Location: Dorint Novotel.
To find the location have a look at the map.

19:00-19:30 Organ Concerto

Prof. Klemens Schnorr at the Marienorgel at the Freiburger Münster.
The four organs of Freiburg Münsterlink were built in 1964/65. Main instrument is the Marienorgel on the left of transept (61 stops, 4 manuals and pedal), built as well as the Choir organ by Rieger, Schwarzach / Austria. The Choir organ was changed in 1990 and translated from the left to the right side. The organ in the main nave is built by Marcussen /Denmark, its organ case is inspired by the original instrument made by Jörg Ebert from Ravensburg in 1545. The16th century sculptures of holy Mary (top) and the trumpet player (bottom) are still conserved. The organ on S.Michael choir in the tower was built by Freiburg organ builder Späth. All four organs with totally 136 stops can be played at the central console in the choir.

19:30-21:30 Welcome Reception

Location: Historical Merchant House, Münsterplatz.
To find the location have a look at the map.

May 21st, 2007

08:00-17:30 Symposium Registration

Location: Convention Center.
To find the location have a look at the map.

08:30-10:30 Session 1: Plenary Opening

- Hans-Joachim Wunderlich : Universität Stuttgart, DE, ETS'07 Vice Program Chair


Welcome Address
Bernd Becker : Universität Freiburg, Germany, ETS'07 General Chair

Technical Program Introduction
Zebo Peng : Linköping University, Sweden, ETS'07 Program Chair

Presentation of ETS'06 Best Paper Award
Erik Jan Marinissen : NXP Research, The Netherlands, ETS'06 Program Chair

09:00-09:45 Keynote

If It's All About Yield, Why Talk About Testing?
Rene Segers : NXP Semiconductors, The Netherlands

09:45-10:30 Invited Address

Electronics Design-For-Test: Past, Present and Future
Ben Bennetts : Bennetts Associates, United Kingdom

10:30-11:00 Coffee 

11:00-12:30 Session 2A: Fault and Defect Diagnosis

- Janusz Rajski : Mentor Graphics, USA
- Laroussi Bouzaida : ST Microelectronics, FR

Adaptive Debug and Diagnosis Without Fault Dictionaries
Stefan HOLST · Hans-Joachim WUNDERLICH : Universität Stuttgart, Germany

Interconnect Open Defect Diagnosis with Minimal Physical Information
Chen LIU : University of Iowa, USA · Wei ZOU : Mentor Graphics, USA · Sudhakar M.REDDY : University of Iowa, USA · Wu-Tung CHENG · Sharma MANISH · Huaxing TANG : Mentor Graphics, USA

DERRIC: a Tool for Unified Logic Diagnosis
Alexandre ROUSSET · Alberto BOSIO · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France

08:30-10:30 Session 2B: Mixed Signal DFT and Test

- Andrew Richardson : University of Lancaster, UK
- Seiji Kajihara : Kyushu Institute of Technology, JP

A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter
Erik SCHÜLER · Marcelo NEGREIROS : Universidade Federal do Rio Grande do Sul, Brazil · Pascal NOUET : LIRMM, France · Luigi CARRO : Universidade Federal do Rio Grande do Sul, Brazil

Reducing the Influence of DC Offset Drift in analog IPs using the Thue-Morse Sequence as Stimulus
Jan SCHAT : NXP, Germany

Using current testing to improve test coverage in mixedsignal IC testing
Yang ZHONG : RWTH Aachen University, Germany · Liquan FANG · Henk VAN DE DONK : NXP Semiconductors, The Netherlands

08:30-10:30 Vendor Session 2C: Advanced DFT Tools

- Peter Muhmenthaler : Infineon Technologies, DE
- Einar J. Aas : Norwegian University of Science & Technology, NO

A Review of Power Strategies for DFT and ATPG
Richard ILLMAN · Brion KELLER · Sandeep BHATIA : Cadence, USA

ScanBurst - Scan Infrastructure and Environment for Highly Effective At-Speed Testing
Stephen PATERAS · Peter SHIELDS : LogicVision, USA

Realizing yield improvements with YieldAssist: High Volume Scan Diagnosis and Analysis
Brady BENWARE : Mentor Graphics, USA

12:30-14:00 Lunch 

14:00-15:30 Session 3A: NoC Testing

- Gert Jervan : Tallinn University of Technology, EE
- Krishnendu Chakrabarty : Duke University, US

Test Configurations for Diagnosing Faulty Links in NoC Switches
Jaan RAIK · Raimund UBAR · Vineeth GOVIND : Tallinn University of Technology, Estonia

Optimization of NoC Wrapper Design Under Bandwidth and Test Time Constraints
Fawnizu Azmadi HUSSIN · Tomokazu YONEDA · Hideo FUJIWARA : Nara Institute of Science and Technology, Japan

How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes?
Xuan-Tu TRAN · Jean DURUPT · François BERTRAND : CEA-LETI, France · Vincent BEROULLE · Chantal ROBACH : INPG-LCIS, France

14:00-15:30 Session 3B: Advances in RF Test

- Jochen Rivoir : Verigy, DE
- Abhijit Chatterjee : Georgia Tech, US

FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests
Ivo KOREN · Frank DEMMERLE · Roland MAY · Martin KAIBEL : Infineon AG, Germany · Sebastian SATTLER : Infineon Technologies, Germany

Digital Generation of Signals for Low Cost RF BIST
Marcelo NEGREIROS · Luigi CARRO · Altamiro SUSIN : Universidade Federal do Rio Grande do Sul, Brazil

Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives
Shaji KRISHNAN · René JONKER · Leon VAN DE LOGT : NXP Semicondutors, The Netherlands

14:00-15:30 Vendor Session 3C: Test Equipment and Solutions

- Yervant Zorian : Virage Logic, US
- Gunnar Carlsson : Ericsson, SE

The FLEX Architecture - High Efficiency Multisite Test
Martin STADLER : Teradyne, Germany

Scalable System Platform for Cost Effective Mixed Signal Test Solutions

Solutions for Testing Complex SoCs
Martin FISCHER : Verigy, Germany

15:30-16:30 Session 4: Posters and Coffee Break

Primary Input Vectors to Eliminate from Random Test Sequences for Synchronous Sequential Circuits
Irith POMERANZ : Purdue University, USA · Sudhakar M.REDDY : University of Iowa, USA

Reducing Test Data Volume of Deterministic BIST Via Test-Point Insertion
Yang ZHAO · Dong XIANG : Tsinghua University, China · Krishnendu CHAKRABARTY : Duke University, USA

A Self-Correction Method for Change in Clock Signal Width
Yukiya MIURA : Tokyo Metropolitan University, Japan

On Improving Channel Utilization in Testing NoC-Based Systems
Jia LI : Chinese Academy of Sciences, China · Qiang XU : The Chinese University of Hong Kong, Hong Kong · Yu HU · Xiao-wei LI : Chinese Academy of Sciences, China

Logic Errors in CMOS circuits due to Simultaneous Switching Noise
Florence AZAÏS · Laurent LARGUIER · Michel RENOVELL : LIRMM, France

Towards a test vector independent test response analyser for NoCs
Kim PETERSEN : HDC AB, Sweden · Johnny ÖBERG : KTH, Sweden

Analysis of Random Testbench for Data-Dominated Hardware Descriptions
Iñigo UGARTE · Pablo SANCHEZ : Universidad de Cantabria, Spain

Accessibility to Embedded A/MS Cores: An Oscillation-Based S-R DFT
Rahebeh NIARAKI : Iran University of Science and Technology, Iran · Zainalabedin NAVABI : Northeastern University, USA · Sattar MIRZAKUCHAKI : Iran University of Science and Technology, Iran · Michel RENOVELL : LIRMM, France

Implementation of security extension for IEEE Std 1149.1 and analysis of possible attack scenarios
Franc NOVAK · Anton BIASIZZO : Jozef Stefan Institute, Slovenia

Pattern Generation for Composite Leakage Current Maximization
Ashesh RASTOGI · Kunal GANESHPURE · Alodeep SANYAL · Sandip KUNDU : University of Massachusetts, USA

16:30-18:00 Session 5A: Diagnosis and Debug

- John P. Hayes : University of Michigan, US
- Bruno Rouzeyre : LIRMM, FR

Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips
Tao XU · Krishnendu CHAKRABARTY : Duke University, USA

Communication-centric SoC Debug using Transactions
Bart VERMEULEN · Kees GOOSSENS : NXP Semiconductors, The Netherlands · Remco VAN STEEDEN : University of Twente, The Netherlands · Martijn BENNEBROEK : Philips Research, The Netherlands

Debug Architecture of the En-II System-on-Chip
Bart VERMEULEN · Sjaak BAKKER : NXP Semiconductors, The Netherlands

16:30-17:30 Session 5B: Simulation and Verification

- Franco Fummi : University Verona, IT
- Jaan Raik : Tallinn University of Technology, EE

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories
Olivier GINEZ : LIRMM, France · Jean-Michel DAGA : ATMEL, France · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France

Test Circuit for Functional Verification of Automatically Generated Cell Library
M. GOMEZ · A. SILVA · S. BAVARESCO · C. ALEGRETTI · G. SARTORI · L. ROSA Jr. : Universidade Federal do Rio Grande do Sul, Brazil · A. REIS : Nangate, USA · Renato RIBAS : Universidade Federal do Rio Grande do Sul, Brazil

16:30-18:00 Vendor Session 5C: Intelligent Test Flows

- Bernd Koenemann : Visiting Professor, Universität Bremen, DE
- Jerzy Tyszer : Poznan University of Technology, PL

Multiple Benefit by Adaptive Testing
Gil BALOG : OptimalTest, Israel

New RF Test Technologies for lower cost and flexibility
Bill BURROWS : Aeroflex Test Solutions, United Kingdom

Enabling DUT-ATE Interaction
Frank GROSSMANN : SPEA, Germany

18:00-19:30 Panel Session 6A: Logic BIST and Test-Data Compression: Friends or Foes?

- Ben Bennetts : Bennetts Associates, UK
- Erik Jan Marinissen : NXP Research, NL

- Ben Bennetts : Bennetts Associates, UK

Abstract:  Just a few years ago, Logic BIST was presented as the one and only solution to virtually all test challenges: growing ATE costs, growing test application times, difficult test access to deeply embedded cores, etc. However, suddenly, in 2001, before mainstream acceptance of Logic BIST, the first commercial Test Data Compression tool was launched. This, and similar TDC products, seemed to have quickly gained foothold in the DfT market. This panel will address the following questions: Did TDC tools actually erode the market for Logic BIST tools? How do TDC and Logic BIST compare, in benefits and costs? Is the success of TDC a temporary thing, while the long-term solution still has to come from Logic BIST? What are companies offering or using today, and how do they expect that to change in the medium- and long-term future? Is the DfT space per chip big enough for both approaches to co-exist?

- Davide Appello : ST Microelectronics, Italy
- Friedrich Hapke : NXP Semiconductors, Germany
- Richard Illman : Cadence Design Systems, United Kingdom
- Steve Sunter : LogicVision, Canada
- Jürgen Alt : Infineon Technologies, Germany
- Janusz Rajski : Mentor Graphics, USA
- Tom Williams : Synopsys, USA

18:00-19:00 Embedded Tutorial Session 6B: 

- Patrick Girard : LIRMM, FR

Low Power Test
Nicola NICOLICI : McMaster University, Canada · Xiaoqing WEN : Kyushu Institute of Technology, Japan

Abstract  Excessive power during test affects the reliability of digital integrated circuits, test throughput and manufacturing yield. Numerous low power test methods have been investigated over the past decade and new power-aware automatic test pattern generation, design-for-test and test planning techniques have emerged. This embeded tutorial introduces the topic of low power test and it overviews the basic techniques and some recent advancements in this field.

20:00-22:00 Dinner 

Location: Feierling
More detailed information can be found here.

May 22nd, 2007

08:00-15:00 Symposium Registration

Location: Convention Center.
To find the location have a look at the map.

8:30-10:00 Session 7A: Memory Test

- Matteo Sonza Reorda : Politecnico di Torino, IT
- Jean-Michel Daga : Atmel, FR

PPM Reduction on Embedded Memories in System on Chip
Said HAMDIOUI · Zaid AL-ARS : Delft University of Technology, The Netherlands · Javier JIMENEZ · Jose CALERO : Design of System on Silicon DS2, Spain

An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
Philipp OEHLER · Sybille HELLEBRAND : Universität Paderborn, Germany · Hans-Joachim WUNDERLICH : Universität Stuttgart, Germany

Dynamic Two-Cell Incorrect Read Fault due to Resistive-Open Defects in the Sense Amplifiers of SRAMs
Alexandre NEY · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France · Magali BASTIAN : Infineon, France

8:30-10:00 Session 7B: Faults, IEEE 1500 and IJTAG/SJTAG

- Nicola Nicolici : McMaster University, CAN
- Elena Gramatova : Slovak Academy of Sciences, SK

Delay Fault Testing of Interconnect Logic Between Embedded Cores
Ramesh TEKUMALLA : Advanced Micro Devices, USA

A Smart Delay Testing Framework based-on IEEE 1500
Po-Lin CHEN · Hao-Hsuan CHIU · Jhih-Wei LIN · Tsin-Yuan CHANG : Tsinghua University, Taiwan

Extended STAPL as SJTAG engine
Johan HOLMQVIST : Linköpings Universitet, Sweden · Gunnar CARLSSON : Ericsson, Sweden · Erik LARSSON : Linköpings Universitet, Sweden

8:30-10:00 Vendor Session 7C: Key Technology: Electrical Contacts

- Joan Figueras : UPC, ES
- Carsten Wegener : Infineon, DE

Probing Challenges for Next Generation SoC Devices
Sergio PEREZ : FormFactor, USA

New Low Inductance Socket Technology for High Speed Memory Device Testing
Joachim MOERBT : Advantest, Germany

Multi-site Test - Extraordinary DFT Desired
Peter MUHMENTHALER : Infineon Technologies, Germany

10:00-11:00 Session 8: Posters and Coffee Break

Defect-Tolerant N2-Transistor Structure for Reliable Design at the Nanoscale
Aiman EL-MALEH : King Fahd University of Petroleum&Minerals, Saudi Arabia · Bashir AL-HASHIMI : University of Southampton, United Kingdom · Ahmad AL-YAMANI : King Fahd University of Petroleum&Minerals, Saudi Arabia

Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure
Satoshi OHTAKE · Kosuke YABUKI · Hideo FUJIWARA : Nara Institute of Science and Technology, Japan

The Effects of Static Test Compaction for Functional Test Sequences on the Coverage of Stuck-at and Transition Faults
Irith POMERANZ : Purdue University, USA · Sudhakar M.REDDY : University of Iowa, USA

Learning from Failure Analysis: a case study
Federico BARONTI · Roberto RONCELLA · Roberto SALETTI : University of Pisa, Italy · Paolo D'ABRAMO · Luca DI PIRO · Monica GIARDI : AustriaMicroSystems, Italy

SAT-based ATPG for Path Delay Faults in Industrial Circuits
Stefan EGGERSGLÜSS · Görschwin FEY · Rolf DRECHSLER : Universität Bremen, Germany · Andreas GLOWATZ · Friedrich HAPKE · Juergen SCHLOEFFEL : NXP Semiconductors, Germany

A Novel Circuit-Oriented SAT Engine and Its Application to Unbounded Model Checking
Yang ZHAO · Tao LV · Lingyi LIU · Hua-wei LI · Xiao-wei LI : Chinese Academy of Sciences, China

A Pattern Selection Approach for Accelerating Soft Error Rate Testing
Alodeep SANYAL · Kunal GANESHPURE · Sandip KUNDU : University of Massachusetts, USA

Reliable Measurement of Interconnect Delays in Presence of Crosstalk-Induced Noise
Michal KOPEC · Tomasz GARBOLINO · Krzysztof GUCWA · Andrzej HLAWICZKA : Silesian University of Technology, Poland

Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories
Tsu-Wei TSENG · Chun-Hsien WU · Jin-Fu LI : National Central University, Taiwan

ADL-driven Test Pattern Generation for Functional Verification of Embedded Processors
Anupam CHATTOPADHYAY : ISS, Germany · Arnab SINHA : CSE, IIT Kharagpur, India · Diandian ZHANG · Rainer LEUPERS · Gerd ASCHEID · Heinrich MEYR : ISS, RWTH Aachen University, Germany

11:00-12:30 Session 9A: On-Line Testing and Self-Test

- Luigi Carro : UFRGS, BR
- Xiaowei Li : Chinese Academy of Science, CN

A novel approach for online sensor testing based on an encoded test stimulus
Norbert DUMAS · Zhou XU · Konstantinos GEORGOPOULOS : Lancaster University, United Kingdom · John BUNYAN : QinetiQ, United Kingdom · Andrew RICHARDSON : Lancaster University, United Kingdom

Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Andreas MERENTITIS · Nektarios KRANITIS · Antonis PASCHALIS : University of Athens, Greece · Dimitris GIZOPOULOS : University of Piraeus, Greece

Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors
Tomoo INOUE · Takashi FUJII · Hideyuki ICHIHARA : Hiroshima City University, Japan

11:00-12:30 Session 9B: Fault Grading and Test Quality

- Joao Paulo Teixeira : IST / INESC-ID, PT
- Hideo Fujiwara : Nara Institute of Science and Technology, JP

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression
Zhanglei WANG · Krishnendu CHAKRABARTY : Duke University, USA · Michael BIENEK : Advanced Micro Devices, USA

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs
Raimund UBAR · Sergei DEVADZE · Jaan RAIK · Artur JUTMAN : Tallinn University of Technology, Estonia

Computation and Application of Absolute Dominators in Industrial Designs
René KRENZ-BAATH · Andreas GLOWATZ · Juergen SCHLOEFFEL : NXP, Germany

11:00-12:30 Vendor Session 9C: Test Communities

- Christian Landrault : LIRMM, FR
- Erik Larsson : Linköping University, SE

Semiconductor Test Consortium Expands its Charter
Klaus LUTZ : Advantest, Germany

STC - New Working Group for Docking and Interfacing
Florian PUTZ : esmo, Germany

The STC's University Working Group Drives Alignment of Industry
Paul RODDY : Semiconductor Test Consortium STC, USA

12:30-14:00 Lunch 

14:00-15:00 Embedded Tutorial Session 10A: 

- Bashir Al-Hashimi : University of Southampton, UK

System-in-Package (SIP), A combination of challenges and solutions
Philippe CAUVET : NXP, France · Serge BERNARD · Michel RENOVELL : LIRMM, France

Abstract  System-in-Package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.

14:00-15:00 Embedded Tutorial Session 10B: 

- Paolo Prinetto : Politecnico di Torino, IT

IC Test Cost Benchmarking
Klaus LUTHER : Infineon Technologies, Germany

Abstract  Driven by the increasing complexity of integrated circuits the pressure on test cost reduction increases exponentially as productivity on chip level progresses according to Moore's Law. A high-level strategic approach for test cost target setting and planning will be explained. The intention is to keep cost of test constant relative to overall cost of goods sold. This method has been developed and used at Infineon over the last couple of years to align our location, equipment and productivity target setting.

14:00-15:00 Embedded Tutorial Session 10C: 

- Hans Kerkhoff : University of Twente, NL

Wafer Level Reliability Screens
Peter MAXWELL : Micron Technology, USA

Abstract  This tutorial discusses test methods and voltage stress appoaches required to ensure effective cost effective defect screening to produce high quality, reliable products. Wafer level reliability screens (WLRS) refers to the application of screens during wafer test that will both activate and detect a sufficient number of defects so that early life failure rate (ELFR) is reduced enough to meet customer spec, preferably without doing burn-in. Further, these screens have to have acceptable yield loss and acceptable test times

15:30-23:30 Social Event

More detailed information can be found here.

May 23rd, 2007

08:00-16:00 Symposium Registration

Location: Convention Center.
To find the location have a look at the map.

8:30-10:00 Session 11A: Diagnosis and Yield Improvement

- Sybille Hellebrand : Universität Paderborn, DE
- Aiman El-Maleh : King Fahd University of Petroleum & Minerals, Saudi Arabia

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement
Huaxing TANG · Sharma MANISH · Janusz RAJSKI · Martin KEIM · Brady BENWARE : Mentor Graphics, USA

Diagnostic Test Generation Based on Subsets of Faults
Irith POMERANZ : Purdue University, USA · Sudhakar REDDY : University of Iowa, USA

Compound Defects Diagnosis with Non-Compressed Patterns
Yu HUANG · Wu-Tung CHENG · Ruifeng GUO : Mentor Graphics, USA

8:30-10:00 Session 11B: Single Event Upsets

- Cecilia Metra : University of Bologna, IT
- José Luis Huertas : IMSE-CNM, ES

Static and Dynamic Analysis of SEU effects in SRAMbased FPGAs
Luca STERPONE · Massimo VIOLANTE : Politecnico di Torino, Italy

Multiple SEU Tolerance in LUTs of FPGAs Using Protected Schemes
Hamid Reza ZARANDI · Seyed Ghassem MIREMADI : Sharif University of Technology, Iran · Costas ARGYRIDES · Dhiraj PRADHAN : University of Bristol, United Kingdom

System level approaches for mitigation of long duration transient faults in future technologies
Carlos LISBOA : Universidade Federal do Rio Grande do Sul, Brazil · Marcelo ERIGSON : Instituto de Informatica UFRGS, Brazil · Luigi CARRO : Universidade Federal do Rio Grande do Sul, Brazil

10:00-11:00 Session 12: Posters and Coffee Break

Exploiting Arithmetic Built-In Self-Test Techniques for Path Delay Fault Testing
Oystein GJERMUNDNES · Einar J. AAS : Norwegian University of Science and Technology, NTNU, Norway

Efficient Search Space Pruning for Multi-Valued SAT based ATPG
Maheshwar CHANDRASEKAR · Michael HSIAO : Virginia Tech, USA

A Defect-Tolerant Architecture for the End of Roadmap CMOS
Maryam ASHOUEI : Georgia Tech, USA · Adit SINGH : Auburn University, USA · Abhijit CHATTERJEE : Georgia Tech, USA

Minimal March Tests for Dynamic Faults in Random Access Memories
Gurgen HARUTYUNYAN · Valery VARDANIAN : Virage Logic, Armenia

An Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory
Costas A ARGYRIDES : University of Bristol, United Kingdom · Hamid Reza ZARANDI : Sharif University of Technology, Iran · Dhiraj PRADHAN : University of Bristol, United Kingdom

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition
Aiman EL-MALEH · Mustafa ALI · Ahmad AL-YAMANI : King Fahd University of Petroleum&Minerals, Saudi Arabia

TAM Design and Test Data Compression for SoC Test Cost Reduction
Julien DALMASSO · Marie-Lise FLOTTES · Bruno ROUZEYRE : LIRMM, France

Bayesian estimation for an imperfect test and repair model
Simon WILSON : Trinity College, Ireland · Suresh GOYAL : Lucent Technologies Bell Labs, USA

Test-Data Compression Based on Variable-to-Variable Reusable Huffman Coding
Chrisovalantis KAVOUSIANOS : University of Ioannina, Greece · Emmanouil KALLIGEROS · Dimitris NIKOLOS : University of Patras, Greece

Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Swtiching
Li ZHENTAO · Shuming CHEN : National University of Defence Technology, China

11:00-12:30 Panel Session 13A: Error Tolerance: Are Good-enough Chips Good Enough?

- Ilia Polian : Universität Freiburg, Germany

- Ilia Polian : Universität Freiburg, DE

Abstract:  The advent of nanoscale technologies is leading to more and more errors, both hard and soft, showing up in the circuits. Known fault tolerance approaches can help in solving the problem, but often at an prohibitively high cost. Error tolerance is a novel paradigm stating that circuits containing defects, or good-enough (rather than perfect) chips, can operate in a way acceptable with respect to an application. First experiments demonstrated that a significant share of single-stuck-at faults in MPEG and JPEG devices lead to an acceptable performance. This panel will address the following questions: Is error tolerance a concept suited to achieve adequate yields in inherently unreliable nanoscale technologies? What are the implications of error tolerance on the design, test and verification flows? Is the market willing to accept good-enough chips? Is error tolerance applicable to hard or soft errors? What are the limitations?

- Rob Aitken : ARM, USA
- Abhijit Chatterjee : Georgia Tech, USA
- Sandip Gupta : University of Southern California, USA
- John P. Hayes : University of Michigan, USA
- Jens Leenstra : IBM R&D, Germany

11:00-12:30 Special Session 13B: Test Access for Chips, Boards and Multi-Board Systems: What is Really Needed?

- Robert Ruiz : Synopsys, USA
- Erik Larsson : Linköping University, Sweden

- Erik Jan Marinissen : NXP Research, NL

Abstract  What do you do when chips on a board behave unexpectedly? How do you know if the errors originate from functional design bugs or physical manufacturing defects? Do you have access to the internal silicon signals for observation and/or stimulation? Can you access the signals even when chips are mounted on boards and placed into systems? Do IJTAG and SJTAG initiatives help with this issue, or is something else needed?

- Bill Eklow : Cisco, USA
- Gunnar Carlsson : Ericsson, Sweden
- Jeff Rearick : AMD, USA
- Bart Vermeulen : NXP, The Netherlands

12:30-14:00 Lunch 

14:00-15:30 Session 14: Delay and Performance Test

- Michel Renovell : LIRMM, FR
- Adam Osseiran : Edith Cowan University, AUS

Automatic generation of instructions to robustly test delay defects in processors
Sankar GURUMURTHY · Ramtilak VEMU · Jacob ABRAHAM : University of Texas, USA · DanielG. SAAB : Case Western Reserve University, USA

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
Paolo BERNARDI · Michelangelo GROSSO · Edgar SÁNCHEZ · Matteo SONZA REORDA : Politecnico di Torino, Italy

Purely Digital BIST for any PLL or DLL
Stephen SUNTER · Aubin ROY : LogicVision, Canada

15:30-15:45 Session 15: Closing Remarks and Introduction to ETS'08

Matteo Sonza Reorda : Politecnico di Torino, Italy ETS'08 General Chair

16:00-19:00 Affiliated Workshop 

- 4th IEEE International Workshop on Silicon Debug and Diagnosis - SDDlink.
To be continued on Thursday, May 24th.