ETS'07 - May 22nd, 2007

- Complete Program
- May 20th, 2007 only
- May 21st, 2007 only
- May 22nd, 2007 only
- May 23rd, 2007 only
- Presentation Sessions only
- Vendor Sessions only
- Posters Sessions only
- Panels Sessions only
- Tutorials only

May 22nd, 2007

08:00-15:00 Symposium Registration

Location: Convention Center.
To find the location have a look at the map.

8:30-10:00 Session 7A: Memory Test

Moderators
- Matteo Sonza Reorda : Politecnico di Torino, IT
- Jean-Michel Daga : Atmel, FR

PPM Reduction on Embedded Memories in System on Chip
Said HAMDIOUI · Zaid AL-ARS : Delft University of Technology, The Netherlands · Javier JIMENEZ · Jose CALERO : Design of System on Silicon DS2, Spain

An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
Philipp OEHLER · Sybille HELLEBRAND : Universität Paderborn, Germany · Hans-Joachim WUNDERLICH : Universität Stuttgart, Germany

Dynamic Two-Cell Incorrect Read Fault due to Resistive-Open Defects in the Sense Amplifiers of SRAMs
Alexandre NEY · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France · Magali BASTIAN : Infineon, France

8:30-10:00 Session 7B: Faults, IEEE 1500 and IJTAG/SJTAG

Moderators
- Nicola Nicolici : McMaster University, CAN
- Elena Gramatova : Slovak Academy of Sciences, SK

Delay Fault Testing of Interconnect Logic Between Embedded Cores
Ramesh TEKUMALLA : Advanced Micro Devices, USA

A Smart Delay Testing Framework based-on IEEE 1500
Po-Lin CHEN · Hao-Hsuan CHIU · Jhih-Wei LIN · Tsin-Yuan CHANG : Tsinghua University, Taiwan

Extended STAPL as SJTAG engine
Johan HOLMQVIST : Linköpings Universitet, Sweden · Gunnar CARLSSON : Ericsson, Sweden · Erik LARSSON : Linköpings Universitet, Sweden

8:30-10:00 Vendor Session 7C: Key Technology: Electrical Contacts

Moderators
- Joan Figueras : UPC, ES
- Carsten Wegener : Infineon, DE

Probing Challenges for Next Generation SoC Devices
Sergio PEREZ : FormFactor, USA

New Low Inductance Socket Technology for High Speed Memory Device Testing
Joachim MOERBT : Advantest, Germany

Multi-site Test - Extraordinary DFT Desired
Peter MUHMENTHALER : Infineon Technologies, Germany

10:00-11:00 Session 8: Posters and Coffee Break

Defect-Tolerant N2-Transistor Structure for Reliable Design at the Nanoscale
Aiman EL-MALEH : King Fahd University of Petroleum&Minerals, Saudi Arabia · Bashir AL-HASHIMI : University of Southampton, United Kingdom · Ahmad AL-YAMANI : King Fahd University of Petroleum&Minerals, Saudi Arabia

Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure
Satoshi OHTAKE · Kosuke YABUKI · Hideo FUJIWARA : Nara Institute of Science and Technology, Japan

The Effects of Static Test Compaction for Functional Test Sequences on the Coverage of Stuck-at and Transition Faults
Irith POMERANZ : Purdue University, USA · Sudhakar M.REDDY : University of Iowa, USA

Learning from Failure Analysis: a case study
Federico BARONTI · Roberto RONCELLA · Roberto SALETTI : University of Pisa, Italy · Paolo D'ABRAMO · Luca DI PIRO · Monica GIARDI : AustriaMicroSystems, Italy

SAT-based ATPG for Path Delay Faults in Industrial Circuits
Stefan EGGERSGLÜSS · Görschwin FEY · Rolf DRECHSLER : Universität Bremen, Germany · Andreas GLOWATZ · Friedrich HAPKE · Juergen SCHLOEFFEL : NXP Semiconductors, Germany

A Novel Circuit-Oriented SAT Engine and Its Application to Unbounded Model Checking
Yang ZHAO · Tao LV · Lingyi LIU · Hua-wei LI · Xiao-wei LI : Chinese Academy of Sciences, China

A Pattern Selection Approach for Accelerating Soft Error Rate Testing
Alodeep SANYAL · Kunal GANESHPURE · Sandip KUNDU : University of Massachusetts, USA

Reliable Measurement of Interconnect Delays in Presence of Crosstalk-Induced Noise
Michal KOPEC · Tomasz GARBOLINO · Krzysztof GUCWA · Andrzej HLAWICZKA : Silesian University of Technology, Poland

Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories
Tsu-Wei TSENG · Chun-Hsien WU · Jin-Fu LI : National Central University, Taiwan

ADL-driven Test Pattern Generation for Functional Verification of Embedded Processors
Anupam CHATTOPADHYAY : ISS, Germany · Arnab SINHA : CSE, IIT Kharagpur, India · Diandian ZHANG · Rainer LEUPERS · Gerd ASCHEID · Heinrich MEYR : ISS, RWTH Aachen University, Germany

11:00-12:30 Session 9A: On-Line Testing and Self-Test

Moderators
- Luigi Carro : UFRGS, BR
- Xiaowei Li : Chinese Academy of Science, CN

A novel approach for online sensor testing based on an encoded test stimulus
Norbert DUMAS · Zhou XU · Konstantinos GEORGOPOULOS : Lancaster University, United Kingdom · John BUNYAN : QinetiQ, United Kingdom · Andrew RICHARDSON : Lancaster University, United Kingdom

Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Andreas MERENTITIS · Nektarios KRANITIS · Antonis PASCHALIS : University of Athens, Greece · Dimitris GIZOPOULOS : University of Piraeus, Greece

Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors
Tomoo INOUE · Takashi FUJII · Hideyuki ICHIHARA : Hiroshima City University, Japan

11:00-12:30 Session 9B: Fault Grading and Test Quality

Moderators
- Joao Paulo Teixeira : IST / INESC-ID, PT
- Hideo Fujiwara : Nara Institute of Science and Technology, JP

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression
Zhanglei WANG · Krishnendu CHAKRABARTY : Duke University, USA · Michael BIENEK : Advanced Micro Devices, USA

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs
Raimund UBAR · Sergei DEVADZE · Jaan RAIK · Artur JUTMAN : Tallinn University of Technology, Estonia

Computation and Application of Absolute Dominators in Industrial Designs
René KRENZ-BAATH · Andreas GLOWATZ · Juergen SCHLOEFFEL : NXP, Germany

11:00-12:30 Vendor Session 9C: Test Communities

Moderators
- Christian Landrault : LIRMM, FR
- Erik Larsson : Linköping University, SE

Semiconductor Test Consortium Expands its Charter
Klaus LUTZ : Advantest, Germany

STC - New Working Group for Docking and Interfacing
Florian PUTZ : esmo, Germany

The STC's University Working Group Drives Alignment of Industry
Paul RODDY : Semiconductor Test Consortium STC, USA

12:30-14:00 Lunch 

14:00-15:00 Embedded Tutorial Session 10A: 

Moderator
- Bashir Al-Hashimi : University of Southampton, UK

System-in-Package (SIP), A combination of challenges and solutions
Philippe CAUVET : NXP, France · Serge BERNARD · Michel RENOVELL : LIRMM, France

Abstract  System-in-Package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.

14:00-15:00 Embedded Tutorial Session 10B: 

Moderator
- Paolo Prinetto : Politecnico di Torino, IT

IC Test Cost Benchmarking
Klaus LUTHER : Infineon Technologies, Germany

Abstract  Driven by the increasing complexity of integrated circuits the pressure on test cost reduction increases exponentially as productivity on chip level progresses according to Moore's Law. A high-level strategic approach for test cost target setting and planning will be explained. The intention is to keep cost of test constant relative to overall cost of goods sold. This method has been developed and used at Infineon over the last couple of years to align our location, equipment and productivity target setting.

14:00-15:00 Embedded Tutorial Session 10C: 

Moderator
- Hans Kerkhoff : University of Twente, NL

Wafer Level Reliability Screens
Peter MAXWELL : Micron Technology, USA

Abstract  This tutorial discusses test methods and voltage stress appoaches required to ensure effective cost effective defect screening to produce high quality, reliable products. Wafer level reliability screens (WLRS) refers to the application of screens during wafer test that will both activate and detect a sufficient number of defects so that early life failure rate (ELFR) is reduced enough to meet customer spec, preferably without doing burn-in. Further, these screens have to have acceptable yield loss and acceptable test times

15:30-23:30 Social Event

More detailed information can be found here.