ETS'07 - Tutorials

- Complete Program
- May 20th, 2007 only
- May 21st, 2007 only
- May 22nd, 2007 only
- May 23rd, 2007 only
- Presentation Sessions only
- Vendor Sessions only
- Posters Sessions only
- Panels Sessions only
- Tutorials only

May 20th, 2007

09:00-10:30 Tutorials

More detailed information can be found here.

10:30-11:00 Coffee 

11:00-12:30 Tutorials

More detailed information can be found here.

12:30-13:30 Lunch 

13:30-15:00 Tutorials

More detailed information can be found here.

15:00-15:30 Coffee 

15:30-17:00 Tutorials

More detailed information can be found here.

May 21st, 2007

10:30-11:00 Coffee 

12:30-14:00 Lunch 

18:00-19:00 Embedded Tutorial Session 6B: 

Moderator
- Patrick Girard : LIRMM, FR

Low Power Test
Nicola NICOLICI : McMaster University, Canada · Xiaoqing WEN : Kyushu Institute of Technology, Japan

Abstract  Excessive power during test affects the reliability of digital integrated circuits, test throughput and manufacturing yield. Numerous low power test methods have been investigated over the past decade and new power-aware automatic test pattern generation, design-for-test and test planning techniques have emerged. This embeded tutorial introduces the topic of low power test and it overviews the basic techniques and some recent advancements in this field.

20:00-22:00 Dinner 

Location: Feierling
More detailed information can be found here.

May 22nd, 2007

12:30-14:00 Lunch 

14:00-15:00 Embedded Tutorial Session 10A: 

Moderator
- Bashir Al-Hashimi : University of Southampton, UK

System-in-Package (SIP), A combination of challenges and solutions
Philippe CAUVET : NXP, France · Serge BERNARD · Michel RENOVELL : LIRMM, France

Abstract  System-in-Package (SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.

14:00-15:00 Embedded Tutorial Session 10B: 

Moderator
- Paolo Prinetto : Politecnico di Torino, IT

IC Test Cost Benchmarking
Klaus LUTHER : Infineon Technologies, Germany

Abstract  Driven by the increasing complexity of integrated circuits the pressure on test cost reduction increases exponentially as productivity on chip level progresses according to Moore's Law. A high-level strategic approach for test cost target setting and planning will be explained. The intention is to keep cost of test constant relative to overall cost of goods sold. This method has been developed and used at Infineon over the last couple of years to align our location, equipment and productivity target setting.

14:00-15:00 Embedded Tutorial Session 10C: 

Moderator
- Hans Kerkhoff : University of Twente, NL

Wafer Level Reliability Screens
Peter MAXWELL : Micron Technology, USA

Abstract  This tutorial discusses test methods and voltage stress appoaches required to ensure effective cost effective defect screening to produce high quality, reliable products. Wafer level reliability screens (WLRS) refers to the application of screens during wafer test that will both activate and detect a sufficient number of defects so that early life failure rate (ELFR) is reduced enough to meet customer spec, preferably without doing burn-in. Further, these screens have to have acceptable yield loss and acceptable test times

May 23rd, 2007

12:30-14:00 Lunch