ETS'07 - Presentation Sessions only

- Complete Program
- May 20th, 2007 only
- May 21st, 2007 only
- May 22nd, 2007 only
- May 23rd, 2007 only
- Presentation Sessions only
- Vendor Sessions only
- Posters Sessions only
- Panels Sessions only
- Tutorials only

May 20th, 2007

10:30-11:00 Coffee 

12:30-13:30 Lunch 

15:00-15:30 Coffee 

May 21st, 2007

10:30-11:00 Coffee 

11:00-12:30 Session 2A: Fault and Defect Diagnosis

Moderators
- Janusz Rajski : Mentor Graphics, USA
- Laroussi Bouzaida : ST Microelectronics, FR

Adaptive Debug and Diagnosis Without Fault Dictionaries
Stefan HOLST · Hans-Joachim WUNDERLICH : Universität Stuttgart, Germany

Interconnect Open Defect Diagnosis with Minimal Physical Information
Chen LIU : University of Iowa, USA · Wei ZOU : Mentor Graphics, USA · Sudhakar M.REDDY : University of Iowa, USA · Wu-Tung CHENG · Sharma MANISH · Huaxing TANG : Mentor Graphics, USA

DERRIC: a Tool for Unified Logic Diagnosis
Alexandre ROUSSET · Alberto BOSIO · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France

08:30-10:30 Session 2B: Mixed Signal DFT and Test

Moderators
- Andrew Richardson : University of Lancaster, UK
- Seiji Kajihara : Kyushu Institute of Technology, JP

A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter
Erik SCHÜLER · Marcelo NEGREIROS : Universidade Federal do Rio Grande do Sul, Brazil · Pascal NOUET : LIRMM, France · Luigi CARRO : Universidade Federal do Rio Grande do Sul, Brazil

Reducing the Influence of DC Offset Drift in analog IPs using the Thue-Morse Sequence as Stimulus
Jan SCHAT : NXP, Germany

Using current testing to improve test coverage in mixedsignal IC testing
Yang ZHONG : RWTH Aachen University, Germany · Liquan FANG · Henk VAN DE DONK : NXP Semiconductors, The Netherlands

12:30-14:00 Lunch 

14:00-15:30 Session 3A: NoC Testing

Moderators
- Gert Jervan : Tallinn University of Technology, EE
- Krishnendu Chakrabarty : Duke University, US

Test Configurations for Diagnosing Faulty Links in NoC Switches
Jaan RAIK · Raimund UBAR · Vineeth GOVIND : Tallinn University of Technology, Estonia

Optimization of NoC Wrapper Design Under Bandwidth and Test Time Constraints
Fawnizu Azmadi HUSSIN · Tomokazu YONEDA · Hideo FUJIWARA : Nara Institute of Science and Technology, Japan

How to Implement an Asynchronous Test Wrapper for Networks-on-Chip Nodes?
Xuan-Tu TRAN · Jean DURUPT · François BERTRAND : CEA-LETI, France · Vincent BEROULLE · Chantal ROBACH : INPG-LCIS, France

14:00-15:30 Session 3B: Advances in RF Test

Moderators
- Jochen Rivoir : Verigy, DE
- Abhijit Chatterjee : Georgia Tech, US

FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests
Ivo KOREN · Frank DEMMERLE · Roland MAY · Martin KAIBEL : Infineon AG, Germany · Sebastian SATTLER : Infineon Technologies, Germany

Digital Generation of Signals for Low Cost RF BIST
Marcelo NEGREIROS · Luigi CARRO · Altamiro SUSIN : Universidade Federal do Rio Grande do Sul, Brazil

Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives
Shaji KRISHNAN · René JONKER · Leon VAN DE LOGT : NXP Semicondutors, The Netherlands

16:30-18:00 Session 5A: Diagnosis and Debug

Moderators
- John P. Hayes : University of Michigan, US
- Bruno Rouzeyre : LIRMM, FR

Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips
Tao XU · Krishnendu CHAKRABARTY : Duke University, USA

Communication-centric SoC Debug using Transactions
Bart VERMEULEN · Kees GOOSSENS : NXP Semiconductors, The Netherlands · Remco VAN STEEDEN : University of Twente, The Netherlands · Martijn BENNEBROEK : Philips Research, The Netherlands

Debug Architecture of the En-II System-on-Chip
Bart VERMEULEN · Sjaak BAKKER : NXP Semiconductors, The Netherlands

16:30-17:30 Session 5B: Simulation and Verification

Moderators
- Franco Fummi : University Verona, IT
- Jaan Raik : Tallinn University of Technology, EE

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories
Olivier GINEZ : LIRMM, France · Jean-Michel DAGA : ATMEL, France · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France

Test Circuit for Functional Verification of Automatically Generated Cell Library
M. GOMEZ · A. SILVA · S. BAVARESCO · C. ALEGRETTI · G. SARTORI · L. ROSA Jr. : Universidade Federal do Rio Grande do Sul, Brazil · A. REIS : Nangate, USA · Renato RIBAS : Universidade Federal do Rio Grande do Sul, Brazil

20:00-22:00 Dinner 

Location: Feierling
More detailed information can be found here.

May 22nd, 2007

8:30-10:00 Session 7A: Memory Test

Moderators
- Matteo Sonza Reorda : Politecnico di Torino, IT
- Jean-Michel Daga : Atmel, FR

PPM Reduction on Embedded Memories in System on Chip
Said HAMDIOUI · Zaid AL-ARS : Delft University of Technology, The Netherlands · Javier JIMENEZ · Jose CALERO : Design of System on Silicon DS2, Spain

An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
Philipp OEHLER · Sybille HELLEBRAND : Universität Paderborn, Germany · Hans-Joachim WUNDERLICH : Universität Stuttgart, Germany

Dynamic Two-Cell Incorrect Read Fault due to Resistive-Open Defects in the Sense Amplifiers of SRAMs
Alexandre NEY · Patrick GIRARD · Christian LANDRAULT · Serge PRAVOSSOUDOVITCH · Arnaud VIRAZEL : LIRMM, France · Magali BASTIAN : Infineon, France

8:30-10:00 Session 7B: Faults, IEEE 1500 and IJTAG/SJTAG

Moderators
- Nicola Nicolici : McMaster University, CAN
- Elena Gramatova : Slovak Academy of Sciences, SK

Delay Fault Testing of Interconnect Logic Between Embedded Cores
Ramesh TEKUMALLA : Advanced Micro Devices, USA

A Smart Delay Testing Framework based-on IEEE 1500
Po-Lin CHEN · Hao-Hsuan CHIU · Jhih-Wei LIN · Tsin-Yuan CHANG : Tsinghua University, Taiwan

Extended STAPL as SJTAG engine
Johan HOLMQVIST : Linköpings Universitet, Sweden · Gunnar CARLSSON : Ericsson, Sweden · Erik LARSSON : Linköpings Universitet, Sweden

11:00-12:30 Session 9A: On-Line Testing and Self-Test

Moderators
- Luigi Carro : UFRGS, BR
- Xiaowei Li : Chinese Academy of Science, CN

A novel approach for online sensor testing based on an encoded test stimulus
Norbert DUMAS · Zhou XU · Konstantinos GEORGOPOULOS : Lancaster University, United Kingdom · John BUNYAN : QinetiQ, United Kingdom · Andrew RICHARDSON : Lancaster University, United Kingdom

Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Andreas MERENTITIS · Nektarios KRANITIS · Antonis PASCHALIS : University of Athens, Greece · Dimitris GIZOPOULOS : University of Piraeus, Greece

Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors
Tomoo INOUE · Takashi FUJII · Hideyuki ICHIHARA : Hiroshima City University, Japan

11:00-12:30 Session 9B: Fault Grading and Test Quality

Moderators
- Joao Paulo Teixeira : IST / INESC-ID, PT
- Hideo Fujiwara : Nara Institute of Science and Technology, JP

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression
Zhanglei WANG · Krishnendu CHAKRABARTY : Duke University, USA · Michael BIENEK : Advanced Micro Devices, USA

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs
Raimund UBAR · Sergei DEVADZE · Jaan RAIK · Artur JUTMAN : Tallinn University of Technology, Estonia

Computation and Application of Absolute Dominators in Industrial Designs
René KRENZ-BAATH · Andreas GLOWATZ · Juergen SCHLOEFFEL : NXP, Germany

12:30-14:00 Lunch 

May 23rd, 2007

8:30-10:00 Session 11A: Diagnosis and Yield Improvement

Moderators
- Sybille Hellebrand : Universität Paderborn, DE
- Aiman El-Maleh : King Fahd University of Petroleum & Minerals, Saudi Arabia

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement
Huaxing TANG · Sharma MANISH · Janusz RAJSKI · Martin KEIM · Brady BENWARE : Mentor Graphics, USA

Diagnostic Test Generation Based on Subsets of Faults
Irith POMERANZ : Purdue University, USA · Sudhakar REDDY : University of Iowa, USA

Compound Defects Diagnosis with Non-Compressed Patterns
Yu HUANG · Wu-Tung CHENG · Ruifeng GUO : Mentor Graphics, USA

8:30-10:00 Session 11B: Single Event Upsets

Moderators
- Cecilia Metra : University of Bologna, IT
- José Luis Huertas : IMSE-CNM, ES

Static and Dynamic Analysis of SEU effects in SRAMbased FPGAs
Luca STERPONE · Massimo VIOLANTE : Politecnico di Torino, Italy

Multiple SEU Tolerance in LUTs of FPGAs Using Protected Schemes
Hamid Reza ZARANDI · Seyed Ghassem MIREMADI : Sharif University of Technology, Iran · Costas ARGYRIDES · Dhiraj PRADHAN : University of Bristol, United Kingdom

System level approaches for mitigation of long duration transient faults in future technologies
Carlos LISBOA : Universidade Federal do Rio Grande do Sul, Brazil · Marcelo ERIGSON : Instituto de Informatica UFRGS, Brazil · Luigi CARRO : Universidade Federal do Rio Grande do Sul, Brazil

12:30-14:00 Lunch 

14:00-15:30 Session 14: Delay and Performance Test

Moderators
- Michel Renovell : LIRMM, FR
- Adam Osseiran : Edith Cowan University, AUS

Automatic generation of instructions to robustly test delay defects in processors
Sankar GURUMURTHY · Ramtilak VEMU · Jacob ABRAHAM : University of Texas, USA · DanielG. SAAB : Case Western Reserve University, USA

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
Paolo BERNARDI · Michelangelo GROSSO · Edgar SÁNCHEZ · Matteo SONZA REORDA : Politecnico di Torino, Italy

Purely Digital BIST for any PLL or DLL
Stephen SUNTER · Aubin ROY : LogicVision, Canada