ETS'07 - May 23rd, 2007

- Complete Program
- May 20th, 2007 only
- May 21st, 2007 only
- May 22nd, 2007 only
- May 23rd, 2007 only
- Presentation Sessions only
- Vendor Sessions only
- Posters Sessions only
- Panels Sessions only
- Tutorials only

May 23rd, 2007

08:00-16:00 Symposium Registration

Location: Convention Center.
To find the location have a look at the map.

8:30-10:00 Session 11A: Diagnosis and Yield Improvement

Moderators
- Sybille Hellebrand : Universität Paderborn, DE
- Aiman El-Maleh : King Fahd University of Petroleum & Minerals, Saudi Arabia

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement
Huaxing TANG · Sharma MANISH · Janusz RAJSKI · Martin KEIM · Brady BENWARE : Mentor Graphics, USA

Diagnostic Test Generation Based on Subsets of Faults
Irith POMERANZ : Purdue University, USA · Sudhakar REDDY : University of Iowa, USA

Compound Defects Diagnosis with Non-Compressed Patterns
Yu HUANG · Wu-Tung CHENG · Ruifeng GUO : Mentor Graphics, USA

8:30-10:00 Session 11B: Single Event Upsets

Moderators
- Cecilia Metra : University of Bologna, IT
- José Luis Huertas : IMSE-CNM, ES

Static and Dynamic Analysis of SEU effects in SRAMbased FPGAs
Luca STERPONE · Massimo VIOLANTE : Politecnico di Torino, Italy

Multiple SEU Tolerance in LUTs of FPGAs Using Protected Schemes
Hamid Reza ZARANDI · Seyed Ghassem MIREMADI : Sharif University of Technology, Iran · Costas ARGYRIDES · Dhiraj PRADHAN : University of Bristol, United Kingdom

System level approaches for mitigation of long duration transient faults in future technologies
Carlos LISBOA : Universidade Federal do Rio Grande do Sul, Brazil · Marcelo ERIGSON : Instituto de Informatica UFRGS, Brazil · Luigi CARRO : Universidade Federal do Rio Grande do Sul, Brazil

10:00-11:00 Session 12: Posters and Coffee Break

Exploiting Arithmetic Built-In Self-Test Techniques for Path Delay Fault Testing
Oystein GJERMUNDNES · Einar J. AAS : Norwegian University of Science and Technology, NTNU, Norway

Efficient Search Space Pruning for Multi-Valued SAT based ATPG
Maheshwar CHANDRASEKAR · Michael HSIAO : Virginia Tech, USA

A Defect-Tolerant Architecture for the End of Roadmap CMOS
Maryam ASHOUEI : Georgia Tech, USA · Adit SINGH : Auburn University, USA · Abhijit CHATTERJEE : Georgia Tech, USA

Minimal March Tests for Dynamic Faults in Random Access Memories
Gurgen HARUTYUNYAN · Valery VARDANIAN : Virage Logic, Armenia

An Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory
Costas A ARGYRIDES : University of Bristol, United Kingdom · Hamid Reza ZARANDI : Sharif University of Technology, Iran · Dhiraj PRADHAN : University of Bristol, United Kingdom

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition
Aiman EL-MALEH · Mustafa ALI · Ahmad AL-YAMANI : King Fahd University of Petroleum&Minerals, Saudi Arabia

TAM Design and Test Data Compression for SoC Test Cost Reduction
Julien DALMASSO · Marie-Lise FLOTTES · Bruno ROUZEYRE : LIRMM, France

Bayesian estimation for an imperfect test and repair model
Simon WILSON : Trinity College, Ireland · Suresh GOYAL : Lucent Technologies Bell Labs, USA

Test-Data Compression Based on Variable-to-Variable Reusable Huffman Coding
Chrisovalantis KAVOUSIANOS : University of Ioannina, Greece · Emmanouil KALLIGEROS · Dimitris NIKOLOS : University of Patras, Greece

Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Swtiching
Li ZHENTAO · Shuming CHEN : National University of Defence Technology, China

11:00-12:30 Panel Session 13A: Error Tolerance: Are Good-enough Chips Good Enough?

Organizer
- Ilia Polian : Universität Freiburg, Germany

Moderator
- Ilia Polian : Universität Freiburg, DE

Abstract:  The advent of nanoscale technologies is leading to more and more errors, both hard and soft, showing up in the circuits. Known fault tolerance approaches can help in solving the problem, but often at an prohibitively high cost. Error tolerance is a novel paradigm stating that circuits containing defects, or good-enough (rather than perfect) chips, can operate in a way acceptable with respect to an application. First experiments demonstrated that a significant share of single-stuck-at faults in MPEG and JPEG devices lead to an acceptable performance. This panel will address the following questions: Is error tolerance a concept suited to achieve adequate yields in inherently unreliable nanoscale technologies? What are the implications of error tolerance on the design, test and verification flows? Is the market willing to accept good-enough chips? Is error tolerance applicable to hard or soft errors? What are the limitations?

Panelists
- Rob Aitken : ARM, USA
- Abhijit Chatterjee : Georgia Tech, USA
- Sandip Gupta : University of Southern California, USA
- John P. Hayes : University of Michigan, USA
- Jens Leenstra : IBM R&D, Germany

11:00-12:30 Special Session 13B: Test Access for Chips, Boards and Multi-Board Systems: What is Really Needed?

Organizers
- Robert Ruiz : Synopsys, USA
- Erik Larsson : Linköping University, Sweden

Moderator
- Erik Jan Marinissen : NXP Research, NL

Abstract  What do you do when chips on a board behave unexpectedly? How do you know if the errors originate from functional design bugs or physical manufacturing defects? Do you have access to the internal silicon signals for observation and/or stimulation? Can you access the signals even when chips are mounted on boards and placed into systems? Do IJTAG and SJTAG initiatives help with this issue, or is something else needed?

Speakers
- Bill Eklow : Cisco, USA
- Gunnar Carlsson : Ericsson, Sweden
- Jeff Rearick : AMD, USA
- Bart Vermeulen : NXP, The Netherlands

12:30-14:00 Lunch 

14:00-15:30 Session 14: Delay and Performance Test

Moderators
- Michel Renovell : LIRMM, FR
- Adam Osseiran : Edith Cowan University, AUS

Automatic generation of instructions to robustly test delay defects in processors
Sankar GURUMURTHY · Ramtilak VEMU · Jacob ABRAHAM : University of Texas, USA · DanielG. SAAB : Case Western Reserve University, USA

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
Paolo BERNARDI · Michelangelo GROSSO · Edgar SÁNCHEZ · Matteo SONZA REORDA : Politecnico di Torino, Italy

Purely Digital BIST for any PLL or DLL
Stephen SUNTER · Aubin ROY : LogicVision, Canada

15:30-15:45 Session 15: Closing Remarks and Introduction to ETS'08

Matteo Sonza Reorda : Politecnico di Torino, Italy ETS'08 General Chair

16:00-19:00 Affiliated Workshop 

- 4th IEEE International Workshop on Silicon Debug and Diagnosis - SDD.
To be continued on Thursday, May 24th.