ETS'07 - Poster Sesions only

- Complete Program
- May 20th, 2007 only
- May 21st, 2007 only
- May 22nd, 2007 only
- May 23rd, 2007 only
- Presentation Sessions only
- Vendor Sessions only
- Posters Sessions only
- Panels Sessions only
- Tutorials only

May 20th, 2007

10:30-11:00 Coffee 

12:30-13:30 Lunch 

15:00-15:30 Coffee 

May 21st, 2007

10:30-11:00 Coffee 

12:30-14:00 Lunch 

15:30-16:30 Session 4: Posters and Coffee Break

Primary Input Vectors to Eliminate from Random Test Sequences for Synchronous Sequential Circuits
Irith POMERANZ : Purdue University, USA · Sudhakar M.REDDY : University of Iowa, USA

Reducing Test Data Volume of Deterministic BIST Via Test-Point Insertion
Yang ZHAO · Dong XIANG : Tsinghua University, China · Krishnendu CHAKRABARTY : Duke University, USA

A Self-Correction Method for Change in Clock Signal Width
Yukiya MIURA : Tokyo Metropolitan University, Japan

On Improving Channel Utilization in Testing NoC-Based Systems
Jia LI : Chinese Academy of Sciences, China · Qiang XU : The Chinese University of Hong Kong, Hong Kong · Yu HU · Xiao-wei LI : Chinese Academy of Sciences, China

Logic Errors in CMOS circuits due to Simultaneous Switching Noise
Florence AZAÏS · Laurent LARGUIER · Michel RENOVELL : LIRMM, France

Towards a test vector independent test response analyser for NoCs
Kim PETERSEN : HDC AB, Sweden · Johnny ÖBERG : KTH, Sweden

Analysis of Random Testbench for Data-Dominated Hardware Descriptions
Iñigo UGARTE · Pablo SANCHEZ : Universidad de Cantabria, Spain

Accessibility to Embedded A/MS Cores: An Oscillation-Based S-R DFT
Rahebeh NIARAKI : Iran University of Science and Technology, Iran · Zainalabedin NAVABI : Northeastern University, USA · Sattar MIRZAKUCHAKI : Iran University of Science and Technology, Iran · Michel RENOVELL : LIRMM, France

Implementation of security extension for IEEE Std 1149.1 and analysis of possible attack scenarios
Franc NOVAK · Anton BIASIZZO : Jozef Stefan Institute, Slovenia

Pattern Generation for Composite Leakage Current Maximization
Ashesh RASTOGI · Kunal GANESHPURE · Alodeep SANYAL · Sandip KUNDU : University of Massachusetts, USA

20:00-22:00 Dinner 

Location: Feierling
More detailed information can be found here.

May 22nd, 2007

10:00-11:00 Session 8: Posters and Coffee Break

Defect-Tolerant N2-Transistor Structure for Reliable Design at the Nanoscale
Aiman EL-MALEH : King Fahd University of Petroleum&Minerals, Saudi Arabia · Bashir AL-HASHIMI : University of Southampton, United Kingdom · Ahmad AL-YAMANI : King Fahd University of Petroleum&Minerals, Saudi Arabia

Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure
Satoshi OHTAKE · Kosuke YABUKI · Hideo FUJIWARA : Nara Institute of Science and Technology, Japan

The Effects of Static Test Compaction for Functional Test Sequences on the Coverage of Stuck-at and Transition Faults
Irith POMERANZ : Purdue University, USA · Sudhakar M.REDDY : University of Iowa, USA

Learning from Failure Analysis: a case study
Federico BARONTI · Roberto RONCELLA · Roberto SALETTI : University of Pisa, Italy · Paolo D'ABRAMO · Luca DI PIRO · Monica GIARDI : AustriaMicroSystems, Italy

SAT-based ATPG for Path Delay Faults in Industrial Circuits
Stefan EGGERSGLÜSS · Görschwin FEY · Rolf DRECHSLER : Universität Bremen, Germany · Andreas GLOWATZ · Friedrich HAPKE · Juergen SCHLOEFFEL : NXP Semiconductors, Germany

A Novel Circuit-Oriented SAT Engine and Its Application to Unbounded Model Checking
Yang ZHAO · Tao LV · Lingyi LIU · Hua-wei LI · Xiao-wei LI : Chinese Academy of Sciences, China

A Pattern Selection Approach for Accelerating Soft Error Rate Testing
Alodeep SANYAL · Kunal GANESHPURE · Sandip KUNDU : University of Massachusetts, USA

Reliable Measurement of Interconnect Delays in Presence of Crosstalk-Induced Noise
Michal KOPEC · Tomasz GARBOLINO · Krzysztof GUCWA · Andrzej HLAWICZKA : Silesian University of Technology, Poland

Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories
Tsu-Wei TSENG · Chun-Hsien WU · Jin-Fu LI : National Central University, Taiwan

ADL-driven Test Pattern Generation for Functional Verification of Embedded Processors
Anupam CHATTOPADHYAY : ISS, Germany · Arnab SINHA : CSE, IIT Kharagpur, India · Diandian ZHANG · Rainer LEUPERS · Gerd ASCHEID · Heinrich MEYR : ISS, RWTH Aachen University, Germany

12:30-14:00 Lunch 

May 23rd, 2007

10:00-11:00 Session 12: Posters and Coffee Break

Exploiting Arithmetic Built-In Self-Test Techniques for Path Delay Fault Testing
Oystein GJERMUNDNES · Einar J. AAS : Norwegian University of Science and Technology, NTNU, Norway

Efficient Search Space Pruning for Multi-Valued SAT based ATPG
Maheshwar CHANDRASEKAR · Michael HSIAO : Virginia Tech, USA

A Defect-Tolerant Architecture for the End of Roadmap CMOS
Maryam ASHOUEI : Georgia Tech, USA · Adit SINGH : Auburn University, USA · Abhijit CHATTERJEE : Georgia Tech, USA

Minimal March Tests for Dynamic Faults in Random Access Memories
Gurgen HARUTYUNYAN · Valery VARDANIAN : Virage Logic, Armenia

An Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory
Costas A ARGYRIDES : University of Bristol, United Kingdom · Hamid Reza ZARANDI : Sharif University of Technology, Iran · Dhiraj PRADHAN : University of Bristol, United Kingdom

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition
Aiman EL-MALEH · Mustafa ALI · Ahmad AL-YAMANI : King Fahd University of Petroleum&Minerals, Saudi Arabia

TAM Design and Test Data Compression for SoC Test Cost Reduction
Julien DALMASSO · Marie-Lise FLOTTES · Bruno ROUZEYRE : LIRMM, France

Bayesian estimation for an imperfect test and repair model
Simon WILSON : Trinity College, Ireland · Suresh GOYAL : Lucent Technologies Bell Labs, USA

Test-Data Compression Based on Variable-to-Variable Reusable Huffman Coding
Chrisovalantis KAVOUSIANOS : University of Ioannina, Greece · Emmanouil KALLIGEROS · Dimitris NIKOLOS : University of Patras, Greece

Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Swtiching
Li ZHENTAO · Shuming CHEN : National University of Defence Technology, China

12:30-14:00 Lunch